1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a dynamic semiconductor memory device having a large data I/O width and capable of speeding up data input/output and reducing power consumption.
2. Description of the Background Art
In correspondence to a partial application such as image processing requiring a high memory bandwidth, a memory cell array structure for implementing a large data I/O width is employed for a semiconductor memory device.
Representatively, a DRAM/logic merged memory having a logic circuit and a DRAM (dynamic random access memory) loaded on the same chip is developed. The DRAM/logic merged memory, not provided with I/O pins and external buses generally present between a processor and a DRAM, is capable of executing data transfer with a high degree of freedom, and implements a large data I/O width by providing a number of data I/O lines capable of simultaneously inputting/outputting data in/from a DRAM array part.
However, such a memory cell array structure for implementing a large data I/O width has the following problems:
When the memory is implemented with a higher degree of integration, the size of the memory cell array is increased to increase the length of data I/O lines for transmitting read/write data as well as parasitic capacitances. Further, the number of simultaneously operating data I/O lines is also increased in order to increase the number of simultaneously input/output data. Thus, the following problems are rendered remarkable:
(1) A wiring delay for read/write data on the data I/O lines are unignorably increased to cause a delay in the access time or the like.
(2) Data writing or data reading is simultaneously executed on a number of data I/O lines, to increase current consumption in the data I/O lines.
An object of the present invention is to speed up data input/output and reduce power consumption in a semiconductor memory device having a large data I/O width.
Briefly stated, the present invention is directed to a semiconductor memory device performing data input/output in response to an address signal, which comprises a memory cell array, a data input/output circuit, a plurality of data lines, a plurality of data line connection switching circuits, a plurality of decoding circuits and a control circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns along first and second directions, and is split into a plurality of memory blocks along the first direction. Any one of the plurality of memory blocks is selected in response to the address signal to be subjected to the data input/output. The data input/output circuit is arranged to be adjacent to one of the plurality of memory blocks along the second direction for executing reading and writing of the data on the memory cell array. The plurality of data lines are provided in common to the plurality of memory blocks along the second direction for transmitting the data between the memory cell array and the data input/output circuit. Each of the plurality of data line connection switching circuit is arranged between adjacent memory blocks for splitting the plurality of data input/output lines into regions corresponding to the respective memory blocks. The plurality of decoding circuits are provided in correspondence to the plurality of memory blocks respectively for executing row selection and column selection responsive to the address signal. The control circuit instructs execution of the row selection and the column selection to each decoding circuit and on-off controls each data line connection switching circuit in response to the address signal.
According to another aspect of the present invention, a semiconductor memory device performing data input/output in response to an address signal comprises a memory cell array, a plurality of decoding circuits and a control circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns along first and second directions, and is split into a plurality of sense amplifier blocks along the first direction. Each of the plurality of sense amplifier blocks is split into a plurality of row blocks along the first direction, and any one of the plurality of row blocks is selected in response to the address signal to be subjected to the data input/output.
Each of the plurality of sense amplifier blocks includes a plurality of pairs of bit lines provided corresponding to the memory cell columns respectively along the second direction in common to the plurality of row blocks, a sense amplifier circuit arranged adjacently to one of the row blocks along the second direction for amplifying data on the plurality of pairs of bit lines, and a plurality of bit line connection switching circuits each arranged between adjacent row blocks for splitting the plurality of pairs of bit lines into regions corresponding to the respective row blocks. The plurality of decoding circuits are provided corresponding to the plurality of row blocks respectively for executing row selection and column selection responsive to the address signal. The control circuit instructs execution of the column selection in a selected row block and turns on each bit line connection switching circuit arranged between the selected row block and the sense amplifier circuit.
According to still another aspect of the present invention, a semiconductor memory device performing data input/output in response to an address signal comprises a memory cell array, a data input/output circuit, a plurality of first data lines, a plurality of intermediate nodes, a plurality of second data lines, a plurality of first data line connection switching circuits, a plurality of second data line connection switching circuits, a plurality of decoding circuits and a control circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns along first and second directions, and is split into a plurality of memory blocks along the first direction. The plurality of memory blocks include first and second memory blocks, either one of which is selected in response to the address signal to be subjected to the data input/output. The data input/output circuit executes reading and writing of the data on the memory cell array. The plurality of (M) first data lines are provided (M: natural number) corresponding to the first memory block along the second direction, and split into a plurality of groups each including N (N: natural number smaller than M) first data lines. The plurality of intermediate nodes are provided in correspondence to the plurality of groups respectively. The plurality of (M) second data lines are provided corresponding to the second memory block along the second direction, and split into a plurality of groups each including N second data lines. One second data line of each group of the plurality of second data lines is connected to corresponding each of the plurality of intermediate nodes. The plurality of first data line connection switching circuits are provided between each of the M first data line and the corresponding intermediate node respectively. The plurality of second data line connection switching circuits are provided between each of the M data lines and the data input/output circuit respectively. The plurality of decoding circuits are provided in correspondence to the plurality of memory blocks respectively for executing row selection and column selection in response to the address signal. The plurality of decoding circuits include a first sub decoding circuit provided corresponding to the first memory block and a second sub decoding circuit provided corresponding to the second memory block. The control circuit instructs execution timings for the row selection and the column selection to the first and second decoding circuits in response to the address signal and one-off controls M first and second data line connection switching circuits.
Accordingly, a principal advantage of the present invention resides in that the data line connection switching circuits split the data input/output lines into the regions corresponding to the respective memory blocks while the data line connection switching circuits can be turned on/off in response to selection of any memory block responsive to the address signal, whereby the operating speed can be increased by precedently executing column selection in a partial memory block or power consumption can be reduced by avoiding driving of the data input/output lines in unnecessary regions.
The bit line connection switching circuits split the bit lines into the regions corresponding to the respective row blocks in the respective sense amplifier blocks while only a bit line connection switching circuit arranged between a row block selected by the address signal and the sense amplifier circuit can be selected and turned on, whereby power consumption can be reduced by avoiding driving of the bit lines in unnecessary regions.
Further, the data line connection switching circuits split the data input/output lines to correspond to the respective memory blocks under a structure requiring N:1 selection of the data input/output lines in the respective memory blocks while the data line connection switching circuits can be turned on/off in response to selection of any memory block responsive to the address signal and column selection can be executed at least in a partial memory block before memory block selection, whereby the data input/output can be speeded up.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.